GreenRio1.0 is a seven-stage RISC-V core that supports dynamic branch prediction and out-of-order execution, as well as a non-blocking data cache. The decode unit separates the CPU’s backend and frontend. During stages 0-3, the predicted PC is determined via gshare and the branch target buffer, with the redirect target PC being obtained from the backend. In stage 4, fetched instructions are placed into a FIFO queue for decoding. Then, the ISA registers are renamed, and the reorder buffer maintains the program order of the instructions, providing precise exception. Dependency checks are performed between instructions to enable dual issuing. During the execution stage, instructions are processed by their corresponding units. Load and store operations involve calculating the address, sending the request to Dcache, and utilizing MSRHs to increase cache bandwidth. In the final stage, results are written back. Each Instruction can graduate once its all preceding instructions have successfully written back their results. The SOC of Greenrio1.0 is adapted from another open project in Google’s MPW6.
GreenRio v2.0 employs a dual-issue 7-stage out-of-order architecture supporting the RV64ICMA unprivileged RISC-V ISA. It also supports Zicsr, Zifencei and Sfence.vma privileged extensions as well as the S, M and U privilege mode. GreenRio 2 is written in openEDA friendly synthesizable Verilog. Synthesized with the latest version of OpenLane, the gate count of a single GreenRio 2.0 CPU pipeline is slightly over 230K on the Skywater 130nm process. The area is 15.87 mm^2 at a frequency of 25 MHz.
GreenRio 2 is an improvement from the previous version 1.0, which has already been validated in the Google/Skywater OpenMPW-7 tapeout November last year. GreeRio 1.0 is already the most complex processor design that has ever been fabricated by all past Google/SkyWater OpenMPW shuttle runs.
With the close collaboration between RIOS and Google along with helps from the OpenEDA tool community, GreenRio 2 pushes the design complexity limit that OpenMPW and OpenEDA flow can handle. It is also a very meaningful project demonstrating building a high-performance processor with complete open-source technologies from architecture, RTL to GDSII possible. And GreenRio2.0 is the first place winner in the inaugural international Code-a-Chip competition.
code：https://github.com/0616ygh/GreenRio2
ISSCC code-a-chip competition：
https://github.com/sscs-ose/sscs-ose-code-a-chip.github.io/tree/main/ISSCC23