RIOS-Lab OpenEDA & OpenPDK

GreenRio

GreenRio1.0 is a seven-stage RISC-V core that supports dynamic branch prediction and out-of-order execution, as well as a non-blocking data cache. The decode unit separates the CPU’s backend and frontend. During stages 0-3, the predicted PC is determined via gshare and the branch target buffer, with the redirect target PC being obtained from the backend. In stage 4, fetched instructions are placed into a FIFO queue for decoding. Then, the ISA registers are renamed, and the reorder buffer maintains the program order of the instructions, providing precise exception. Dependency checks are performed between instructions to enable dual issuing. During the execution stage, instructions are processed by their corresponding units. Load and store operations involve calculating the address, sending the request to Dcache, and utilizing MSRHs to increase cache bandwidth. In the final stage, results are written back. Each Instruction can graduate once its all preceding instructions have successfully written back their results. The SOC of Greenrio1.0 is adapted from another open project in Google’s MPW6.

GreenRio v2.0 employs a dual-issue 7-stage out-of-order architecture supporting the RV64ICMA unprivileged RISC-V ISA. It also supports Zicsr, Zifencei and Sfence.vma privileged extensions as well as the S, M and U privilege mode. GreenRio 2 is written in openEDA friendly synthesizable Verilog. Synthesized with the latest version of OpenLane, the gate count of a single GreenRio 2.0 CPU pipeline is slightly over 230K on the Skywater 130nm process. The area is 15.87 mm^2 at a frequency of 25 MHz.

GreenRio 2 is an improvement from the previous version 1.0, which has already been validated in the Google/Skywater OpenMPW-7 tapeout November last year. GreeRio 1.0 is already the most complex processor design that has ever been fabricated by all past Google/SkyWater OpenMPW shuttle runs.

With the close collaboration between RIOS and Google along with helps from the OpenEDA tool community,  GreenRio 2 pushes the design complexity limit that OpenMPW and OpenEDA flow can handle. It is also a very meaningful project demonstrating building a high-performance processor with complete open-source technologies from architecture, RTL to GDSII possible. And GreenRio2.0 is the first place winner in the inaugural international Code-a-Chip competition.

code：https://github.com/0616ygh/GreenRio2

ISSCC code-a-chip competition：

https://github.com/sscs-ose/sscs-ose-code-a-chip.github.io/tree/main/ISSCC23

RIOS-Lab Open-source Hardware IP Research

Microprocessor Patent Research

Tremendous attractions for RISC-V have driven needs for its effective adoption by industry due to its superb free, open, modular and secure nature, as well as its simple and elegant core and large international community. However, during the development of RISC-V, potential patent infringement and implement litigation might occur at processor architecture and microarchitecture. Thus, a secured legal infrastructure against patent troll and pitfalls contributes significantly to the growth of RISC-V community, and it’s also one of the key tools our RIOS Lab is building under the guidance of technical experts. We systematically analyzed thousands of patents from MIPS and ARM, and established a new classification system, RPC (RIOS Patent Classification), in favor of CPU domain knowledge which the existing systems IPC and CPC are in lack of, based on different technical and functional modules during processor design and development process, statistical landscape analysis results of which outshined those based on IPC and CPC. Based on these RPC categories and resources from Google Patent, RIOS Lab also built its own microprocessor-domain patent database infrastructure with machine learning and artificial intelligence (AI) assisted patent recommendation engine.

In addition, legal status, patent assignment, active patents owners, application and grant rate, imminent expiration, number of citations and independent claims, and litigation cases were all investigated.  Through this work RIOS Lab would dedicate a defensive and monitoring system against potential IP risks for RISC-V processor and open-source hardware implementations, and make patent freedom and open source safely achieved in RISC-V ecosystem.

You can find more information about RPC classification here:

https://github.com/RIOS-Laboratory/RIOS-Patent-Classificationhttps://gitcode.net/RIOS_Laboratory/rpc_rios-patent-classification
RIOS-Lab Compiler Design & Optimization

Binary Translation

The RISC-V architecture has gained significant attention in recent years due to its open-source nature and potential for widespread adoption. However, one of the main challenges in adopting RISC-V is the lack of a mature software ecosystem compared to established architectures such as ARM and x86. The binary translation is an effective methodology that can address such challenge.

We thus propose a novel binary translator to automatically convert existing applications of ARM or x86 to RISC-V. The translator is designed to facilitate the adoption of RISC-V architecture by providing a seamless transition of existing software to RISC-V. The use of LLVM IR as a bridge between the source and target architectures allows us to leverage the mature LLVM toolchain and facilitate the translation process. LLVM IR provides a high-level representation of the code that is independent of the source and target architectures, making it easier to translate between different architectures. This reduces the complexity of the translation process and makes it more efficient. Our approach is based on a new paradigm that can automatically learn and generate the mapping rules of assembly instructions. The mapping rules are learned from a large dataset of existing software, which allows the translator to accurately and efficiently translate the software. To ensure the performance of the translated code, we have adopted the SBT paradigm. The SBT paradigm allows us to selectively optimize the performance-critical parts of the code, while leaving the non-critical parts unoptimized. This approach reduces the overall time and effort required to optimize the code while still maintaining the performance of the translated software.

RIOS-Lab Faculties

Weiwei Chen

Weiwei Chen

Research Ccientist of RIOS-Lab

Associate professor, supervisor of postgraduate, former member of Youth Innovation Promotion Association of Chinese Academy of Sciences Senior member of the Optical Engineering Society of China

Expert of the Zhongguancun Cloud Computing Industry Alliance Former chief scientist of artificial intelligence company (CTO level), and former first leader of the 3D NAND chip design team of China. 20+ years of IC industry experience, 7+ years of AI industry experience, led the team to complete 30+ chip/IP core design, served as the technical leader of 5+ National Major Projects, and supervised 30+ students. 70+ Patents(CN and US), software copyrights and articles.

Research Interests

Main research interests for computing in memory chip architecture and design technology, AI chip design nano-memory IC design methodology, and EDA design methodology

Honors and Title

  • Senior member of the Optical Engineering Society of China
  • Expert of Zhongguancun Cloud Computing Industry Alliance
  • Expert of the Intelligent Computing Industry Technology Innovation Consortium
  • Former member of Youth Innovation Promotion Association of Chinese Academy of Sciences
  • Top 10 Scientific Researchers (IMECAS)

Contact

Education

Bachelor of Electronic Science and Technology, Department of Electronics Engineering, Tsinghua University

M.S. in Microelectronics, Tsinghua University, Institute of Microelectronics

PhD in Microelectronics, University of Chinese Academy of Sciences, Institute of Microelectronics

RIOS-Lab Faculties

Lei Ren

Lei Ren

Research Scientist in RIOS Lab

He graduated from Department of Physics at Peking University in 2004 with B.Sc. degree and excellent achievements, during which he was granted Chun-Tsung fellowship and performed initial research on semiconductor nanowire devices successfully as an undergraduate student under its support. He graduated from the Applied Physics program in Department of Electrical and Computer Engineering at Rice University in 2011 with Ph.D. degree. There he performed thorough research on opto-electrical properties of carbon nanoscale devices and their potential applications on computer systems and terahertz optical frequency range, and published multiple high-quality first-author papers on top SCI journals, such as Physical Review B and Nano Letters. He successfully invented carbon nanotube terahertz polarizer, and completed the opto-electrical characterizations on highly aligned single-wall carbon nanotubes, and then laid their groundwork for their potential device applications in computer hardware systems. He was one of the last-class students of the carbon nanotechnology pioneer, Dr. Richard E. Smalley, the 1996 Nobel laureate. He full-time worked in the top technology companies in the energy industry and high-precision optics industry in USA after his Ph.D. graduation until 2022 summer, thereafter he came back to China and started the new career as a research scientist at the RISC-V international open-source laboratory (RIOS Lab) in Tsinghua-Berkeley Shenzhen Institute (TBSI), with research areas focused on semiconductor microprocessor open-source EDA, semiconductor nanoscale device modeling and its multi-physics, and hardware open-source legal patent AI classifications.

Research Interests

Semiconductor microprocessor open-source EDA, Semiconductor nanoscale device modeling and its multi-physics, Hardware open-source legal patent AI classifications

Contact

Education

Peking University, Bechlor 2000-2004

Rice University, Doctor, 2004-2011

RIOS-Lab Faculties

Zhangxi Tan

Zhangxi Tan

Co-Director

Dr. Zhangxi Tan is the Co-Director of the RISC-V International Open-Source Laboratory (RIOS Lab) at Tsinghua-Berkeley Shenzhen Institute (TBSI), and serves as Adjunct Professor, who specializes in computer architecture and VLSI designs. Additionally, Dr. Tan is also the Founder and President of RiVAI Technologies Co. LTD.

Prior to these roles, Dr. Tan joined Pure Storage (NYSE: PSTG) as the company’s first chip designer, where he held leadership roles as a Founding Engineer and Lead Designer. Dr. Tan successfully guided the delivery of the award-winning product (AI Summit 2017, San Francisco), FlashBladeTM, which he grew from infancy to a matured product yields hundreds of million-dollars revenues every year, customers were including: Tesla, Mercedes F1 Racing Team, and Riot Games.

Dr. Tan holds more than 20 US patents in flash storage systems and hardware accelerators, and he is also the inventor of the FPGA-based architecture simulator (RAMP Gold). Dr. Tan has Bachelor and Master degrees in electrical engineering and computer science from Tsinghua University; Master and PhD degrees in computer science from University of California, Berkeley, where he was supervised by Prof. David Patterson, the 2017 Turing Award winner for inventing the reduced instruction set computer (RISC) approach.

Research Interests

My primary research is computer architecture and networks, microprocessor and VLSI designs, open-source RISC-V technologies and ecosystems, OpenEDA and PDK, non-volatile memory systems, SW/HW co-design, implementation of computer systems and generative AI on chip designs. 

Graduate Techings

Readings in Computer Systems, TBSI                                 2020 – 2023

Advanced Micro Processor Processor Design, TBSI                     2020 – 2023

Contact

Education

1998.9 – 2002.7 Department of Electronic Engineering, Tsinghua University, China

2002.9 – 2005.1 Department of Computer Science and Technology, Tsinghua University, China

2005.8 – 2013.7 Computer Science Division, University of California, Berkeley, CA 94720

PhD in Computer Science, minor in Management of Technology

2013.7 – 2013.10 Computer Science Division, University of California, Berkeley, CA 94720

Postdoc Researcher in the ASPIRE lab (aspire.eecs.berkeley.edu)

RIOS-Lab Uncategorized

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RIOS-Lab Events

RISC-V Academic Seminar

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David Patterson RISC-V Open-Source Laboratory and a team led by Zhang Zesong from City University of Hong Kong will have a one-day closed-door academic seminar on March 17, 2023. Students from RIOS Lab and City University of Hong Kong have demonstrated, exchanged, and discussed the latest research progress in RISC-V, which will be an important step for international cooperation on open-source innovation in the Greater Bay Area.

Organizer:

RISC-V International Open-Source Laboratory

City University of Hong Kong

Meeting Agenda:
Time: March 17th.  9:00-15:00

Original link:

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RIOS-Lab News

RIOS Lab Students Won the 1st Place in the First “Code-A-Chip” Competition of ISSCC 2023!

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2/19 – 2/23
San Francisco, CA

The International Solid-State Circuits Conference (ISSCC) is the foremost global forum for presentation of advances in solid-state circuits and systems-on-a-chip.

Fig.1 Group photo of the winning teams and organizers.

The Code-a-Chip competition was sponsored by the CHIPS Alliance and Google.

The student team of the RISC-V Open Source (RIOS) Lab, is the first place winner in the inaugural international Code-a-Chip competition. They presented their project GreenRio 2 at the ISSCC 2023, along with 6 other design teams from around the world. GreenRio 2 is an open-source Linux-compatible RISC-V processor developed using a complete open-source flow.

Fig.2 “Code-a-chip” winner list

Fig.3 Rob Mains, General Manager, CHIPS Alliance
Tim Ansell, General Manager, Google OpenPDK/EDA
Dr. Zhangxi Tan, Co-director, RIOS Lab

Never before has such a large global community gathered together to come up with a complete open RISC-V instruction set providing a solid foundation for architecture and silicon innovations. With the advent of openEDA and openPDK, building an open microprocessor that can run lots of real software is possible with a pure open-source tool and manufacturing flow.

Because of the maturity and limited support of openEDA, many microprocessors taped out in the past 600+ designs on Google OpenMPWs are only 32-bit MCU-class simple processors. RIOS Rio series RISC-V processors (open source under the Apache 2.0 license) on the other hand include all necessary architecture and performance features to run a full 64-bit operating system like Linux and many real-world software.

At ISSCC, RIOS team presented the design of GreenRio 2, and its open-source design flow. GreenRio 2 is an improvement from the previous version 1.0, which has already been validated in the Google/Skywater OpenMPW-7 tapeout November last year. GreeRio 1.0 is already the most complex processor design that has ever been fabricated by all past Google/SkyWater OpenMPW shuttle runs.

Fig.4 Architecture of GreenRio v2.0

Figure 4 shows the microarchitecture of the GreenRio 2 CPU pipeline. It employs a dual-issue 7-stage out-of-order architecture supporting the RV64ICMA unprivileged RISC-V ISA. It also supports Zicsr, Zifencei and Sfence.vma privileged extensions as well as the S, M and U privilege mode. GreenRio 2 is written in openEDA friendly synthesizable Verilog.

Synthesized with the latest version of OpenLane, the gate count of a single GreenRio 2.0 CPU pipeline is slightly over 230K on the Skywater 130nm process. The area is 15.87 mm^2 at a frequency of 25 MHz.

With the close collaboration between RIOS and Google along with helps from the OpenEDA tool community, GreenRio 2 pushes the design complexity limit that OpenMPW and OpenEDA flow can handle. It is also a very meaningful project demonstrating building a high-performance processor with complete open-source technologies from architecture, RTL to GDSII possible.

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RIOS-Lab News

RIOS Lab Released the Official Test Suite Standard for RISC-V Vector Extension at RISC-V Summit

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RISC-V 2022 North America Global Summit

The four-days RISC-V 2022 North America Global Summit was held in San Jose, California, December 12th-15th, 2022. The conference schedule includes:

· RISC-V members day meeting

· RISC-V Future Watch featuring breaking news on products, technology, ecosystem expansion, etc.

· Technical and industry topics meetings

· Innovative research presentation

Automatic Test Generation and Verification for RISC-V Vector Extension, from RISC-V International Open Source (RIOS) laboratory, was admitted by RISC-V Summit North America 2022. Dr. Wang Yi and Mr. Hu Shenwei were honored to attend the conference as speakers and had an in-depth discussion online to communicate with industry professionals.

The RISC-V Vector Extended Instruction Set (RVV) version 1.0 has been introduced for high-performance execution of vectorized computing. However, the RVV introduces 217 new instructions, seven new CSRS, and seven configuration parameters. The complexity makes it difficult for developers to produce a test suite, especially because of the number of different RVV parameter configurations (vlen, vsew, vmul, etc.) that combine with each other.

To solve this problem, RIOS Lab, in collaboration with the RISC-V Foundation, designed an RVV test generator for RISC-V community that can be configured with a combination of parameters. We first designed and implemented the RVV Sail Model as the golden model for executing RVV instructions. With Sail model ‘s support, we further developed a configurable test generator that generates quantifiable coverage test sets for RISC-V vector extensions. The user can select the instruction to be tested, set the configuration parameter combination, and then automatically generate the associated tests.

The whole process of test production and usage is compatible with the latest RISCOF toolchain and can be tested simultaneously with vector extension and other extension test sets in the same environment. We also demonstrated our RVV support for RISCV-ISAC and RISCOF to obtain quantitative coverage reports.

Currently, the Sail RVV adaptation has pushed the Pull Request to the official repository and is being checked by RISC-V Foundation. The test generator and RISC-V ISAC are undergoing final feedback and adjustment with RISC-V  Foundation, and it will be released soon after the improvement.

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