RIOS Lab has finished software package porting and stage3 tarball building for the generic RISC-V board.

RIOS Lab has submitted 100+ commits for the upstream community, and given support for RISC-V architecture.

RIOS Lab was a part of the upstreaming effort for the RISC-V port of V8, implementing the RISC-V ‘C’ extension. The ‘C’ extension optimized the V8 engine by reducing compiled code size. The RISC-V port of V8 has already been pushed to the official V8 upstream repository in February 2021. Please refer to our project roadmap and workgroups for … Continue reading Chrome Browser V8 Engine Porting

RIOS Lab cooperate with the RISC-V foundation and design a configurable RVV test generator for the RISC-V community. We first designed and implemented the RVV Sail Model as the golden model to execute the RVV instructions. We also employ Spike for cross-validation of RVV program executions as compared to our Sail model. After massive iterations … Continue reading RVV Sail Model