With a joint effort between Futurewei Technologies and the RIOS lab, v8-riscv, a RISC-V 64-bit backend for V8 was open-sourced in July. V8-riscv enables the complete functionality of V8 (including the Turbofan compiler, the Ignition Engine and the WebAssembly compiler) for any RISC-V ISA that supports RV64I, M, A, F, D and Zifencei extensions. The functional completeness of a V8 port is measured by the coverage of the extensive set of V8 test cases. Currently, v8-riscv passes over 15,000 standard v8 test cases as well as standard benchmarks such as Sunspider and Kraken on HiFive Unleashed running Fedora Developer Rawhide.
The open-sourcing of v8-riscv pushes our porting effort to a new phase of community participation. There is still plenty of work ahead in bringing a high-performing V8 engine that leverages the full capability of a highly customizable RISC-V ISA. For the next few months, we would like to focus on upstreaming to V8, improving the performance of the 64-bit backend, and supporting or experimenting with additional RISC-V extensions such as C, V, and the upcoming J extensions. Please refer to our project roadmap and workgroups for more details.
We invite any community members who would like to contribute to V8 on RISC-V to join our effort. We already have a good story to share: within the first week of open-sourcing v8-riscv, the PLCT lab of Chinese Academy of Sciences, who has worked on another independent port of V8 for RISC-V, decided to consolidate the porting effort and join v8-riscv.